-Day 1 : PLD and ALTERA FPGA
Introduction to ALTERA Products (Based on MAXII,CycloneII/Cyclone III ,
STRATIXIII/STRATIX IV devices) & Designing with Quartus II Software
-Day 2 : Quartus II design
Using TriMatrix Memories
Clock Management & PLL Capabilities
Designing with DSP Blocks
Use Quartus II software features to understand how design was processed
RTL Viewer
Technology Map Viewers
State Machine Viewer
Chip Planner
Resource Property Editors
Configuration Methods
-Day 3 : Analysis and Debugging of Compilation Result
Analyzing Designs Using Quartus II
Timing analysis using TimeQuest Timing Analyzer.
Board debugging using SignalTap II Embedded Logic Analyzer
VHDL Basic with ALTERA Quartus II
1. Description
Quartus II Basic
This training will give you a basic introduction to programmable logic
devices,
focusing on FPGAs. By exploring the history of programmable logic
technologies,
you’ll learn about the architectural features that make up an FPGA device.
You will see the advantages of using FPGAs for digital logic design.
Finally,
you’ll understand how design software, such as the Altera Quartus II
software,
makes it easy to create and implement digital logic designs.
VHDL Basic
This class is a general introduction to the VHDL language and its use in programmable logic design. The emphasis is on the synthesis constructs of VHDL; however, you will also learn about the simulation constructs. You will gain a basic understanding of VHDL to enable you to begin creating your design file. In the hands-on laboratory sessions, you will put this knowledge to the test by writing simple but practical designs. You will also learn the basic instructions needed for operating both the synthesis and simulation tools of
the Quartus II software.
2.Agenda
-Day 1 : Quartus II Basic
Introduction Basic Device Architecture (Max II & Cyclone II & Stratix II)
Introduction Designing with Quartus II
Quartus II Design Environments
Design Methodology Overview
Basic HDL Design Flow
Design Methodology
Design Entry
Compilation
Simulation in Quartus II
-Day 2 : VHDL Basic
VHDL Design Units
Architecture Modeling
Signal Assignments
Concurrent Statements
Combinatorial Logic Design Method
Sequential Statements
Process Statement
Signals vs Variables
-Day 3 : VHDL Basic
Sequential Logic Design Method
Behavioral vs Structural Modeling
Hierarchical Design Method
Component Instantiation
FSM Design Method
Inference vs Instantiation
Designing Nios II with SOPC Builder and Software Builder Tools(SBT)
1. Description
This course will let you know how to design embedded systems at FPGA
with
Altera soft-core processor(NIOS II).In this course, you can understand
NIOS II. And you can create the NIOS II system using SOPC builder and
software using Nios II Studio. Also, you can know how to interface your
logic designs to the NIOS II system with SIF(System Interconnect Fabric).
This course has a lot of labs and test boards. You can see and debug the
operation of your embedded designs in test boards.When you come back
to work, you can use easily the NIOS II soft-core processor.
2. Agenda
-Day 1 : Nios II development Flow
Nios II Hardware Development
Understanding and Generating NIOS Hardware with peripherals
Nios II Software Development
Building Debugging Software for NIOS
-Day 2 : Nios II System architecture implementation
System Interconnect Fabric
Connecting Custom Peripherals
Custom Instructions
Configuring the target Board
Programming Flash and H/W and S/W booting
